oneAPI Developer Summit at IWOCL 2021

Join us for the first 2021 oneAPI Developer Summit at IWOCL focused on oneAPI and Data Parallel C++ for accelerated computing across xPU architectures (CPU, GPU, FPGA, and other accelerators). In this one-day virtual conference, you will hear from industry and academia speakers working on innovative cross-platform, multi-vendor architecture solutions developed on oneAPI. Learn from fellow developers and connect with other innovators. Please join us, a self-sustained, vibrant community to support each other using oneAPI and Data Parallel C++.

This event will take place on April 26th, 2021.

Schedule: April 26th

Schedule: April 26th

10:00 – 10:10 AM CET INTRODUCTION  
10:10 – 10:50 AM CET

VENDOR UPDATE

SYCL 2021 Vendor Update

Ronan Keryell
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Ronan Keryell

Ronan Keryell

Ronan Keryell is principal software engineer at Xilinx Research Labs. He works on SYCL C++-based programming models for heterogeneous system like FPGA and CGRA. He is the specification editor of the SYCL standard, member of the SYCL, SPIR & OpenCL standard committees from Khronos Group & ISO C++ committee. Ronan Keryell received his MSc in Electrical Engineering and PhD in Computer Science in 1992 from École Normale Supérieure of Paris & University of Paris Sud (France), on the design of a massively parallel RISC-based VLIW-SIMD graphics computer and its programming environment.

Aksel Alpay
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Aksel Alpay

Aksel Alpay

Aksel Alpay is a researcher and software engineer from Heidelberg University, where he works on high performance computing topics. In particular, he is the creator and lead developer of the hipSYCL SYCL implementation, and also engages within the Khronos SYCL working group to advance the language.

Peter Žužek
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Peter Žužek

Peter is a Senior Software Engineer at Codeplay where he has worked on the ComputeCpp runtime and is now the Team Lead of the SYCL-ECO team responsible for maintaining ComputeCpp and providing support for customer and open-source SYCL projects. He has also contributed to the SYCL 1.2.1 and SYCL 2020 specifications and continues to be involved in the SYCL Working Group in Khronos.

Steffen Larsen
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Steffen Larsen

Staff Software Engineer at Codeplay, Steffen has been working on DPC++ for CUDA since early in its development. With SYCL 2020 released and interest for SYCL on the rise, Steffen and his team at Codeplay are working to bring SYCL 2020 feature support to DPC++ for CUDA as they are implemented in DPC++

Igor Vorobtsov
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Igor Vorobtsov

Igor Vorobtsov has more than 15 years of experience in the areas of C/C++ and Fortran compilers, application tuning and developer support. Igor got a Master of Science degree in Applied Mathematics. Since joining Intel in 2008, Igor has worked as a Technical Consulting Engineer supporting software developers throughout EMEA region. Igor has a broad array of application experience, including enterprise applications and high performance computing environments.

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10:50 – 11:20 AM CET

DEVCLOUD UPDATE

Developer tools to get you started on oneAPI

Henry A Gabb
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Henry Gabb

Henry A Gabb

Henry A. Gabb is a Senior Principal Engineer in Intel’s Architecture, Graphics, and Software group. Much of his career has been spent promoting the value of parallel computing, now focusing on oneAPI for heterogeneous parallelism. He is the editor of The Parallel Universe, Intel’s quarterly magazine for software innovation.

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11:20 – 12:50 AM CET

HANDS-ON SESSION

Application optimization with Cache-aware Roofline Model and Intel oneAPI tools

Aleksandar Ilic
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Aleksandar Ilic

Aleksandar Ilic

Aleksandar Ilic is an Assistant Professor at the Instituto Superior Técnico (IST), Universidade de Lisboa, and a Senior Researcher of the INESC-ID, Lisbon, Portugal. He has contributed to more than 50 international journal and conference publications, and received several Excellence in Teaching awards. Besides his teaching experience, he has organized and participated in more than 20 roofline-related tutorials, invited talks and seminars held at different scientific events, such as SC, ISC-HPC, PACT etc. The integration of his scientific contribution (Cache-aware Roofline Model) in industry software tools (Intel Advisor) received the HiPEAC Tech Transfer award for 2017. His research interests include high-performance and energy-efficient computing and modeling of parallel heterogeneous systems.

Diogo Marques
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Diogo Marques

Diogo Marques

Diogo Marques is currently pursuing his Ph.D. degree in Electrical and Computer Engineering at the Instituto Superior Técnico (IST), Universidade de Lisboa, Lisbon, Portugal. He is also a member of the HPCAS research group at Instituto de Engenharia de Sistemas e Computadores R&D (INESC-ID). His current research interests include insightful modeling of multi-core processors and heterogeneous systems. His work contributed to improve the accuracy and insightfulness of roofline modeling based on Cache-aware Roofline Model, by proposing the memory impact metrics and roof scaling methodology presented in Intel Advisor framework.

Rafael Campos
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Rafael Campos

Rafael Campos obtained his MSc degree in Electrical and Computer Engineering from Instituto Superior Técnico (IST), Universidade de Lisboa in 2019. He is currently a young researcher at Instituto de Engenharia de Sistemas e Computadores R&D (INESC-ID), as a part of the HPCAS group. His main interests are performance modeling of heterogeneous systems and GPUs. His work includes performance optimization of bioinformatics applications and roofline modeling of high-performance heterogeneous CPU/GPU systems.

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12:50 – 1:10 PM CET LUNCH  
1:10 – 1:40 PM CET

TECH TALK

AI > A Deep Dive into a Deep Learning Library for the A64FX Fugaku CPU – Meet the Developer

Kentaro Kawakami
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Kentaro Kawakami

Kentaro Kawakami

Kentaro Kawakami is the Senior Researcher at Platform Innovation project, Fujitsu Laboratories Ltd. He joined Fujitsu Laboratories in 2007. He has been involved in R&D of image codec LSIs and wireless sensor nodes, and is currently engaged in R&D of AI software for Arm HPC. His department is involved in researching and developing techniques to accelerate deep learning (DL) processes on Fugaku, PRIMEHPC FX1000/700 and GPU-based supercomputers. His GitHub account name is “kawakami-k”. Kawakami-san lives in Japan and loves cats.

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1:40 – 2:10 AM CET

LIGHTNING TALK

Great Cross-Architecture Challenge Application Showcase

Andrew Pastrello
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Andrew Pastrello

Andrew Pastrello is a PhD student at UNSW Sydney and a nuclear engineer at the Australian Nuclear Science and Technology Organisation. His research is in performance portable Monte Carlo neutron transport algorithms, and he is interested in programming new computer architectures.

Zhen Ju
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Zhen Ju

Zhen Ju gets his master’s degree from the University of the Chinese Academy of Sciences(UCAS) in 2016, and now is a Ph.D. candidate at UCAS, and he is major in computer science. Zhen Ju research in the fields of high-performance computing and heterogeneous acceleration. He has experience in accelerate codes on heterogeneous devices. He has developed an application that can remove redundancy sequences from biological sequences by CUDA and migrated it to One API.

Eugenio Marinelli
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Eugenio Marinelli

Eugenio Marinelli is currently a Ph.D. student in the Data Science Department at EURECOM in Sophia Antipolis (France). He received its master’s degree in Computer Engineering from the Politecnico di Torino in April 2021. His research interests include hardware acceleration for DNA data storage and HPC. 

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2:10 – 2:40 PM CET

KEYNOTE

SYCL 2020 in hipSYCL: DPC++ features on AMD GPUs, NVIDIA GPUs and CPUs

Aksel Alpay
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Aksel Alpay

Aksel Alpay

Aksel Alpay is a researcher and software engineer from Heidelberg University, where he works on high performance computing topics. In particular, he is the creator and lead developer of the hipSYCL SYCL implementation, and also engages within the Khronos SYCL working group to advance the language.

LEARN MORE
2:40 - 3:00 PM CET

LIGHTNING TALK

Bringing SYCL to Super Computers with Celerity

Biagio Cosenza
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Biagio Cosenza

Biagio Cosenza

Biagio Cosenza is an AIM Assistant Professor at the Department of Computer Science, University of Salerno, Italy and associated with TU Berlin, leading the DFG project CELERITY. He was a Postdoctoral Researcher at the University of Innsbruck, Austria, received his Ph.D. from the University of Salerno in 2011, while visiting HLRS and the University of Stuttgart. He has been recipient of several grants and scholarships (HPC-Europa2, HPC-Europa++, DAAD, ISCRA) and authored more than 40 publications. He is currently a member of the Khronos SYCL working group and unit leader for the EuroHPC project LIGATE.

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3:00 – 3:10 PM CET BREAK  
3:10 - 3:30 PM CET

LIGHTNING TALK

Great Cross-Architecture Challenge Application Showcase

Ricardo Nobre
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Ricardo Nobre

Ricardo Nobre received the Ph.D. degree in Informatics Engineering from Faculdade de Engenharia da Universidade do Porto (FEUP), Porto, Portugal, in 2017. He is currently a Researcher at Instituto de Engenharia de Sistemas e Computadores R&D (INESC-ID), Lisbon, Portugal. His interests include high-performance computing, compilers, parallel programming and machine learning. He has contributed close to 20 papers in international journals and conferences.

Rafael Campos
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Rafael Campos

Rafael Campos obtained his MSc degree in Electrical and Computer Engineering from Instituto Superior Técnico (IST), Universidade de Lisboa in 2019. He is currently a young researcher at Instituto de Engenharia de Sistemas e Computadores R&D (INESC-ID), as a part of the HPCAS group. His main interests are performance modeling of heterogeneous systems and GPUs. His work includes performance optimization of bioinformatics applications and roofline modeling of high-performance heterogeneous CPU/GPU systems.

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3:30 – 4:00 PM CET

TECH TALK

It’s Acceleration but Faster! A Business Perspective on FPGA Development.

David James
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David James

David James

Dave leads CSS. He has substantial expertise in systems engineering and technology together with wide project and general management experience leading to a number of world firsts. He has a passion for team working, high expectations and superior performance. He is also a co-founder and Chairman of Porous Liquid Technologies Ltd.

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4:00 – 4:30 PM CET

TECH TALK

Migrating and tuning a CUDA-based stencil computation to DPC++

Clícia S. Pinto
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Clícia S. Pinto

Clícia S. Pinto

Clícia S. Pinto is a Senior Performance Engineer at the Supercomputing Center for Industrial Innovation of SENAI CIMATEC focusing on algorithm development for scientific computing and code optimization, applied to industry and academia. She holds a Ph.D. in Computer Science from Federal University of Bahia and her primary research interests include High-Performance Computing and Data-intensive Computing.​

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4:30 - 4:45 PM CET BREAK  
4:45 - 5:15 PM CET

TECH TALK

Comparative Analysis of Intel HLS Design Tools on a Case Study in Neuromorphic

Luke Kljucaric
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Luke Kljucaric

Luke Kljucaric

I am a PhD student (predoctoral fellow) in computer and electrical engineering at the University of Pittsburgh and a lead student in the HPC group at SHREC. I have been focusing on FPGA and HPC research in the NSF Center for Space, High-Performance, and Resilient Computing (SHREC) to better understand the capabilities of current FPGA design tools, with a specific emphasis on high-level design. The target application of my research is accelerated machine learning, which includes algorithms such as CNNs and neuromorphic-classification algorithms studied on CPUs, GPUs, TPUs, VPUs, and FPGAs.

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5:15 - 5:45 PM CET

TECH TALK

TAU Performance System

Prof. Sameer Shende
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Prof. Sameer Shende

Prof. Sameer Shende

Sameer Shende serves as a Research Associate Professor and the Director of the Performance Research Laboratory at the University of Oregon and the President and Director of ParaTools, Inc. (USA) and ParaTools, SAS (France). He serves as the lead developer of the Extreme-scale Scientific Software Stack (E4S), TAU Performance System, Program Database Toolkit (PDT), and HPC Linux. His research interests include scientific software stacks, performance instrumentation, compiler optimizations, measurement, and analysis tools for HPC. He leads the SDK project for the Exascale Computing Project (ECP), in the Programming Models and Runtime (PMR) area. He serves as the General Co-Chair for ICPP 2021 and the Tech Papers Vice Chair for the SC22 conference. He received his B.Tech. in Electrical Engineering from IIT Bombay in 1991, and his M.S. and Ph.D. in Computer and Information Science from the University of Oregon in 1996 and 2001 respectively.

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5:45 – 6:00 PM CET CLOSING  
6:00 – 7:00 PM CET HAPPY HOUR  

oneAPI Developer Summit at IWOCL 2021 Speakers

Aksel Alpay
Aksel Alpay

Keynote, SYCL 2021 Vendor Update

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Aksel Alpay

Aksel Alpay

Aksel Alpay is a researcher and software engineer from Heidelberg University, where he works on high performance computing topics. In particular, he is the creator and lead developer of the hipSYCL SYCL implementation, and also engages within the Khronos SYCL working group to advance the language.

Prof. Sameer Shende
Prof. Sameer Shende

TAU Performance System

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Prof. Sameer Shende

Prof. Sameer Shende

Sameer Shende serves as a Research Associate Professor and the Director of the Performance Research Laboratory at the University of Oregon and the President and Director of ParaTools, Inc. (USA) and ParaTools, SAS (France). He serves as the lead developer of the Extreme-scale Scientific Software Stack (E4S), TAU Performance System, Program Database Toolkit (PDT), and HPC Linux. His research interests include scientific software stacks, performance instrumentation, compiler optimizations, measurement, and analysis tools for HPC. He leads the SDK project for the Exascale Computing Project (ECP), in the Programming Models and Runtime (PMR) area. He serves as the General Co-Chair for ICPP 2021 and the Tech Papers Vice Chair for the SC22 conference. He received his B.Tech. in Electrical Engineering from IIT Bombay in 1991, and his M.S. and Ph.D. in Computer and Information Science from the University of Oregon in 1996 and 2001 respectively.

Aleksandar Ilic
Aleksandar Ilic

Application optimization with Cache-aware Roofline Model and Intel oneAPI tools

×
Aleksandar Ilic

Aleksandar Ilic

Aleksandar Ilic is an Assistant Professor at the Instituto Superior Técnico (IST), Universidade de Lisboa, and a Senior Researcher of the INESC-ID, Lisbon, Portugal. He has contributed to more than 50 international journal and conference publications, and received several Excellence in Teaching awards. Besides his teaching experience, he has organized and participated in more than 20 roofline-related tutorials, invited talks and seminars held at different scientific events, such as SC, ISC-HPC, PACT etc. The integration of his scientific contribution (Cache-aware Roofline Model) in industry software tools (Intel Advisor) received the HiPEAC Tech Transfer award for 2017. His research interests include high-performance and energy-efficient computing and modeling of parallel heterogeneous systems.

Diogo Marques
Diogo Marques

Application optimization with Cache-aware Roofline Model and Intel oneAPI tools

×
Diogo Marques

Diogo Marques

Diogo Marques is currently pursuing his Ph.D. degree in Electrical and Computer Engineering at the Instituto Superior Técnico (IST), Universidade de Lisboa, Lisbon, Portugal. He is also a member of the HPCAS research group at Instituto de Engenharia de Sistemas e Computadores R&D (INESC-ID). His current research interests include insightful modeling of multi-core processors and heterogeneous systems. His work contributed to improve the accuracy and insightfulness of roofline modeling based on Cache-aware Roofline Model, by proposing the memory impact metrics and roof scaling methodology presented in Intel Advisor framework.

Rafael Campos

Application optimization with Cache-aware Roofline Model and Intel oneAPI tools

×

Rafael Campos

Rafael Campos obtained his MSc degree in Electrical and Computer Engineering from Instituto Superior Técnico (IST), Universidade de Lisboa in 2019. He is currently a young researcher at Instituto de Engenharia de Sistemas e Computadores R&D (INESC-ID), as a part of the HPCAS group. His main interests are performance modeling of heterogeneous systems and GPUs. His work includes performance optimization of bioinformatics applications and roofline modeling of high-performance heterogeneous CPU/GPU systems.

Clícia S. Pinto
Clícia S. Pinto

Migrating and tuning a CUDA-based stencil computation to DPC++

×
Clícia S. Pinto

Clícia S. Pinto

Clícia S. Pinto is a Senior Performance Engineer at the Supercomputing Center for Industrial Innovation of SENAI CIMATEC focusing on algorithm development for scientific computing and code optimization, applied to industry and academia. She holds a Ph.D. in Computer Science from Federal University of Bahia and her primary research interests include High-Performance Computing and Data-intensive Computing.​

Henry Gabb
Henry A Gabb

Developer tools to get you started on oneAPI

×
Henry Gabb

Henry A Gabb

Henry A. Gabb is a Senior Principal Engineer in Intel’s Architecture, Graphics, and Software group. Much of his career has been spent promoting the value of parallel computing, now focusing on oneAPI for heterogeneous parallelism. He is the editor of The Parallel Universe, Intel’s quarterly magazine for software innovation.

Kentaro Kawakami
Kentaro Kawakami

AI > A Deep Dive into a Deep Learning Library for the A64FX Fugaku CPU – Meet the Developer

×
Kentaro Kawakami

Kentaro Kawakami

Kentaro Kawakami is the Senior Researcher at Platform Innovation project, Fujitsu Laboratories Ltd. He joined Fujitsu Laboratories in 2007. He has been involved in R&D of image codec LSIs and wireless sensor nodes, and is currently engaged in R&D of AI software for Arm HPC. His department is involved in researching and developing techniques to accelerate deep learning (DL) processes on Fugaku, PRIMEHPC FX1000/700 and GPU-based supercomputers. His GitHub account name is “kawakami-k”. Kawakami-san lives in Japan and loves cats.

Luke Kljucaric
Luke Kljucaric

Comparative Analysis of Intel HLS Design Tools on a Case Study in Neuromorphic

×
Luke Kljucaric

Luke Kljucaric

I am a PhD student (predoctoral fellow) in computer and electrical engineering at the University of Pittsburgh and a lead student in the HPC group at SHREC. I have been focusing on FPGA and HPC research in the NSF Center for Space, High-Performance, and Resilient Computing (SHREC) to better understand the capabilities of current FPGA design tools, with a specific emphasis on high-level design. The target application of my research is accelerated machine learning, which includes algorithms such as CNNs and neuromorphic-classification algorithms studied on CPUs, GPUs, TPUs, VPUs, and FPGAs.

David James
David James

It’s acceleration ….. but faster! – a business perspective on FPGA technology​

×
David James

David James

Dave leads CSS. He has substantial expertise in systems engineering and technology together with wide project and general management experience leading to a number of world firsts. He has a passion for team working, high expectations and superior performance. He is also a co-founder and Chairman of Porous Liquid Technologies Ltd.

Biagio Cosenza
Biagio Cosenza

Bringing SYCL to Super Computers with Celerity

×
Biagio Cosenza

Biagio Cosenza

Biagio Cosenza is an AIM Assistant Professor at the Department of Computer Science, University of Salerno, Italy and associated with TU Berlin, leading the DFG project CELERITY. He was a Postdoctoral Researcher at the University of Innsbruck, Austria, received his Ph.D. from the University of Salerno in 2011, while visiting HLRS and the University of Stuttgart. He has been recipient of several grants and scholarships (HPC-Europa2, HPC-Europa++, DAAD, ISCRA) and authored more than 40 publications. He is currently a member of the Khronos SYCL working group and unit leader for the EuroHPC project LIGATE.

Ronan Keryell
Ronan Keryell

SYCL 2021 Vendor Update

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Ronan Keryell

Ronan Keryell

Ronan Keryell is principal software engineer at Xilinx Research Labs. He works on SYCL C++-based programming models for heterogeneous system like FPGA and CGRA. He is the specification editor of the SYCL standard, member of the SYCL, SPIR & OpenCL standard committees from Khronos Group & ISO C++ committee. Ronan Keryell received his MSc in Electrical Engineering and PhD in Computer Science in 1992 from École Normale Supérieure of Paris & University of Paris Sud (France), on the design of a massively parallel RISC-based VLIW-SIMD graphics computer and its programming environment.

James Reinders
James Reinders

SYCL 2021 Vendor Update

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James Reinders

James Reinders

James Reinders is a senior engineer who joined Intel Corporation in 1989 and has contributed to projects including systolic arrays systems WARP and iWarp, and the world’s first TeraFLOP supercomputer (ASCI Red), as well as compilers and architecture work for multiple Intel processors and parallel systems. James has been a driver behind the development of Intel as a major provider of software development products, and serves as their chief software evangelist. His most recent book is Data Parallel C++, Mastering DPC++ for Programming of Heterogeneous Systems using C++ and SYCL.

Andrew Richards
Andrew Richards

SYCL 2021 Vendor Update

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Andrew Richards

Andrew Richards

CEO and co-founder of Codeplay, Andrew started his career writing video games in the days of 8-bit computers, progressing to become a lead games programmer at Eutechnyx™, where he wrote best-selling titles such as Pete Sampras Tennis and Total Drivin’. Codeplay has been producing compilers for games consoles, special-purpose processors and GPUs since then. As well as being CEO and Founder of Codeplay Software Ltd, Andrew is also the Chair of the Software working group of the HSA Foundation™ and former Chair of the SYCL™ for OpenCL™ sub-group of the Khronos® Group. Andrew graduated from Cambridge University with a degree in Computer Science and Physics.

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Steffen Larsen

Staff Software Engineer at Codeplay, Steffen has been working on DPC++ for CUDA since early in its development. With SYCL 2020 released and interest for SYCL on the rise, Steffen and his team at Codeplay are working to bring SYCL 2020 feature support to DPC++ for CUDA as they are implemented in DPC++

Peter Žužek

SYCL 2021 Vendor Update

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Peter Žužek

Peter is a Senior Software Engineer at Codeplay where he has worked on the ComputeCpp runtime and is now the Team Lead of the SYCL-ECO team responsible for maintaining ComputeCpp and providing support for customer and open-source SYCL projects. He has also contributed to the SYCL 1.2.1 and SYCL 2020 specifications and continues to be involved in the SYCL Working Group in Khronos.

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